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Add UART transmitter module and testbench

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- Implemented the uart_tx module for UART transmission with configurable clock frequency and baud rate.
- Added a testbench (uart_tx_tb) to verify the functionality of the uart_tx module, including signal generation for start, data, and clock.
- Created a backup of the previous testbench (uart_tx_tb_old) for reference.
This commit is contained in:
Gamenight77
2025-04-17 10:56:16 +02:00
parent d46530f32d
commit 55f9161dfa
14 changed files with 40177 additions and 0 deletions
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72
Semaine 1/UART/uart_rx.v Normal file
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module uart_rx (
input wire clk,
input wire rx, // signal reçues
output reg [7:0] data, // Données decoder
output reg valid = 0, // Indicateur de données valides
output reg ready = 1 // Indicateur de réception prête
);
parameter CLK_FREQ = 27_000_000;
parameter BAUD_RATE = 115_200;
localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
localparam IDLE = 2'b00;
localparam START = 2'b01;
localparam DATA = 2'b10;
localparam STOP = 2'b11;
reg [1:0] state = IDLE;
reg [3:0] bit_index;
reg [15:0] clk_count;
reg [7:0] rx_data = 0;
always @(posedge clk) begin
case (state)
IDLE: begin
ready <= 1;
if (!rx) begin // start bit (0)
state <= START;
clk_count <= 0;
bit_index <= 0;
valid <= 0;
ready <= 0;
end
end
START: begin
if (clk_count < (BIT_PERIOD + (BIT_PERIOD / 2)) - 1) begin
clk_count <= clk_count + 1;
end else begin
clk_count <= 0;
state <= DATA; // Passer à l'état de réception des données après le start bit
end
end
DATA: begin
if (clk_count < BIT_PERIOD - 1) begin
clk_count <= clk_count + 1;
end else begin
clk_count <= 0;
rx_data[bit_index] <= rx; // Recevoir les données (8 bits)
bit_index <= bit_index + 1;
if (bit_index == 7) begin
state <= STOP; // Passer à l'état d'arrêt
end
end
end
STOP: begin
if (clk_count < BIT_PERIOD - 1) begin
clk_count <= clk_count + 1;
end else begin
state <= IDLE;
data <= rx_data;
valid <= 1;
ready <= 1;
end
end
endcase
end
endmodule