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Add UART transmitter module and testbench

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- Implemented the uart_tx module for UART transmission with configurable clock frequency and baud rate.
- Added a testbench (uart_tx_tb) to verify the functionality of the uart_tx module, including signal generation for start, data, and clock.
- Created a backup of the previous testbench (uart_tx_tb_old) for reference.
This commit is contained in:
Gamenight77
2025-04-17 10:56:16 +02:00
parent d46530f32d
commit 55f9161dfa
14 changed files with 40177 additions and 0 deletions
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74
Semaine 1/UART/uart_tx.v Normal file
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module uart_tx(
input wire clk,
input wire start, // Signal de démarrage de la transmission
input wire [7:0] data, // Données à transmettre
output reg tx = 1, // Sortie de transmission
output reg busy = 0 // Indicateur de transmission en cours
);
parameter CLK_FREQ = 27_000_000;
parameter BAUD_RATE = 115_200;
localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
localparam IDLE = 2'b00;
localparam START = 2'b01;
localparam DATA = 2'b10;
localparam STOP = 2'b11;
reg [1:0] state = IDLE;
reg [3:0] bit_index = 0;
reg [15:0] clk_count = 0;
reg [7:0] tx_data = 0;
always @(posedge clk) begin
case(state)
IDLE: begin
busy <= 0;
tx <= 1;
if (start && !busy) begin
tx_data <= data;
bit_index <= 0;
clk_count <= 0;
busy <= 1;
state <= START;
end
end
START: begin
if (clk_count < BIT_PERIOD - 1) begin
clk_count <= clk_count + 1;
tx <= 0;
end else begin
state <= DATA;
clk_count <= 0;
end
end
DATA: begin
if (clk_count < BIT_PERIOD - 1) begin
clk_count <= clk_count + 1;
end else if (bit_index < 8) begin
tx <= tx_data[bit_index];
bit_index <= bit_index + 1;
clk_count <= 0;
end else begin
state <= STOP;
end
end
STOP: begin
tx <= 1;
if (clk_count < BIT_PERIOD - 1) begin
clk_count <= clk_count + 1;
end else begin
clk_count <= 0;
busy <= 0;
state <= IDLE;
end
end
endcase
end
endmodule