Enhance ultrasonic_fpga module: add comment to clarify FSM behavior in the Verilog file

2025-04-22 14:40:12 +02:00
parent 2be0cb20f6
commit 5f3568ff9b
1 changed files with 1 additions and 1 deletions
--- a/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v
+++ b/Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v
@@ -34,7 +34,7 @@ module ultrasonic_fpga #(
    reg [31:0] wait_counter;


-    always @(posedge clk) begin
+    always @(posedge clk) begin // FSM
        
        case (state)
            IDLE: begin