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Enhance ultrasonic_fpga module: add comment to clarify FSM behavior in the Verilog file

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Gamenight77
2025-04-22 14:40:12 +02:00
parent 2be0cb20f6
commit 5f3568ff9b
1 changed files with 1 additions and 1 deletions
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Semaine_1/Capteur_recule_bidirectionel/Ultrasonic/ultrasonic_fpga.v
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@@ -34,7 +34,7 @@ module ultrasonic_fpga #(
reg [31:0] wait_counter; reg [31:0] wait_counter;
always @(posedge clk) begin always @(posedge clk) begin // FSM
case (state) case (state)
IDLE: begin IDLE: begin