Update TX data assignment in UART loopback module to send fixed value

2025-05-07 18:05:02 +02:00
parent f990a6f6d3
commit 6bb42700f8
1 changed files with 1 additions and 1 deletions
--- a/Semaine_4/UART/src/verilog/top_uart_loopback.v
+++ b/Semaine_4/UART/src/verilog/top_uart_loopback.v
@@ -50,7 +50,7 @@ module top_uart_loopback (
                delay_counter <= 0;

                if (rx_received && tx_ready) begin
-                    tx_data <= rx_data;
+                    tx_data <= 8'h31; // Valeur à envoyer
                    state <= WAIT;

                    leds[0] <= 0;