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Add UART TX module and testbench, update scripts and constraints

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Gamenight77
2025-05-05 15:23:44 +02:00
parent e0a54fb42a
commit 7156abf4e7
9 changed files with 145 additions and 0 deletions
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19
Semaine_4/FIFO/constraints/top_uart_loopback.cst Normal file
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IO_LOC "rx" 70;
IO_PORT "rx" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "tx" 69;
IO_PORT "tx" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clk" 4;
IO_PORT "clk" PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "leds[0]" 15;
IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" 16;
IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[2]" 17;
IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[3]" 18;
IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[4]" 19;
IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[5]" 20;
IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;