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forked from tanchou/Verilog

Add UART TX module and testbench, update scripts and constraints

This commit is contained in:
Gamenight77
2025-05-05 15:23:44 +02:00
parent e0a54fb42a
commit 7156abf4e7
9 changed files with 145 additions and 0 deletions

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@call c:\oss-cad-suite\environment.bat
@echo off
if "%1"=="sim" call scripts\simulate.bat
if "%1"=="wave" call scripts\gtkwave.bat
if "%1"=="clean" call scripts\clean.bat
if "%1"=="build" call scripts\build.bat