1
0
forked from tanchou/Verilog

Add UART TX module and testbench, update scripts and constraints

This commit is contained in:
Gamenight77
2025-05-05 15:23:44 +02:00
parent e0a54fb42a
commit 7156abf4e7
9 changed files with 145 additions and 0 deletions

View File

@@ -0,0 +1,4 @@
@echo off
echo === Nettoyage du dossier runs ===
rd /s /q runs
mkdir runs