Add UART TX module and testbench, update scripts and constraints

Semaine_4/FIFO/src/verilog/fifo.v

@@ -0,0 +1,16 @@
+ module uart_tx #(
+	parameter       DETPH = 16,
+	parameter       WIDTH = 8
+)(
+    input wire              clk,
+    input wire              wr_en,
+    input wire[WIDTH-1:0]   wr_data,
+    input wire              rd_en,
+    output wire[WIDTH-1:0]  rd_data,
+
+    output wire             full,
+    output wire             empty,
+);
+
+    
+endmodule