forked from tanchou/Verilog
Add testbench for top_ultrasonic_led module
- Created a new testbench file `top_ultrasonic_led_tb.vvp` to simulate the `top_ultrasonic_led` module. - Defined the necessary signals and events for testing the ultrasonic sensor functionality. - Implemented the main test sequence including triggering the ultrasonic sensor and monitoring the output LEDs based on distance measurements. - Included timing and state management for accurate simulation of the ultrasonic sensor behavior.
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Semaine 1/Capteur_recule/Ultrasonic/ultrasonic.vcd
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Semaine 1/Capteur_recule/Ultrasonic/ultrasonic.vcd
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