counter

2025-03-22 09:50:52 +01:00
parent 8e7615d669
commit 7bd92ebe98
2 changed files with 46 additions and 0 deletions
--- a/Introduction/counter/counter.v
+++ b/Introduction/counter/counter.v
@@ -0,0 +1,16 @@
+module counter (
+    input wire clk,
+    input wire rst,
+    output reg [3:0] count
+    );
+
+    always @(posedge clk)
+    begin
+        if(rst)
+            count <= 4'b0000;
+        else
+            count <= count + 1;
+    end
+);
+    
+endmodule