counter

Introduction/counter/counter.v

@@ -0,0 +1,16 @@
+module counter (
+    input wire clk,
+    input wire rst,
+    output reg [3:0] count
+    );
+
+    always @(posedge clk)
+    begin
+        if(rst)
+            count <= 4'b0000;
+        else
+            count <= count + 1;
+    end
+);
+    
+endmodule

Introduction/counter/tb_counter.v

@@ -0,0 +1,30 @@
+module tb_counter;
+    reg clk;
+    reg rst;
+    wire [3:0] count;
+    
+    counter counter_inst(
+        .clk(clk),
+        .rst(rst),
+        .count(count)
+    );
+
+    always #5 clk = ~clk;
+    
+    initial begin
+        
+        clk <= 0;
+        rst <= 0;
+
+
+        #20 rst = 1;
+        #80 rst = 0;
+        #50 rst = 1;
+
+        #20 $finish;
+    end
+    
+    always begin
+        #5 clk = ~clk;
+    end
+endmodule