Add UART communication modules and testbenches

- Implemented rx_fifo module for receiving data with FIFO management.
- Created tb_top_uart_rx_tx testbench for testing UART transmission and reception.
- Developed tb_uart_rx testbench for validating UART receiver functionality.
- Added tb_uart_tx testbench for testing UART transmitter behavior.
- Designed top_led_uart module to interface UART with LED outputs.
- Integrated top_uart_ultrasonic module for ultrasonic sensor data transmission via UART.
- Implemented tx_fifo module for transmitting data with FIFO management.
- Developed uart_rx module for receiving serial data with state machine control.
- Created uart_top module to connect RX and TX functionalities with FIFO buffers.
- Implemented uart_tx module for transmitting serial data with state machine control.

Semaine_3/UARTV2/uart_top.v

@@ -0,0 +1,86 @@
+module uart_top(
+    input  wire       clk,
+    input  wire       rst,
+    
+    input  wire       uart_rx,
+    output wire       uart_tx,
+    
+    // Interfaces RX vers utilisateur
+    output wire [7:0] rx_data,
+    output wire       rx_data_valid,
+    input  wire       rx_data_ready,
+
+    // Interfaces TX depuis utilisateur
+    input  wire [7:0] tx_data,
+    input  wire       tx_data_valid,
+    output wire       tx_data_ready
+);
+
+    parameter CLK_FRE  = 27_000_000; // Hz
+    parameter UART_FRE = 115200;     // Baudrate
+
+    // === Signaux internes ===
+    wire [7:0] uart_rx_data;
+    wire       uart_rx_data_valid;
+    wire       uart_rx_data_ready;
+
+    wire [7:0] uart_tx_data;
+    wire       uart_tx_data_valid;
+    wire       uart_tx_data_ready;
+
+    // === FIFO RX ===
+    rx_fifo #(
+        .WIDTH(8),
+        .DEPTH(16)
+    ) rx_fifo_inst (
+        .clk            (clk),
+        .rst_p          (rst),
+        .rx_data_in     (uart_rx_data),
+        .rx_data_valid  (uart_rx_data_valid),
+        .rx_data_out    (rx_data),
+        .rx_data_ready  (rx_data_ready),
+        .fifo_empty     (), // pas utilisé ici
+        .fifo_full      ()
+    );
+
+    // === FIFO TX ===
+    tx_fifo #(
+        .WIDTH(8),
+        .DEPTH(16)
+    ) tx_fifo_inst (
+        .clk            (clk),
+        .rst_p          (rst),
+        .tx_data_in     (tx_data),
+        .tx_data_valid  (tx_data_valid),
+        .tx_data_ready  (tx_data_ready),
+        .tx_data_out    (uart_tx_data),
+        .uart_tx_ready  (uart_tx_data_ready)
+    );
+
+    // === Instanciation RX UART ===
+    uart_rx #(
+        .CLK_FRE(CLK_FRE),
+        .BAUD_RATE(UART_FRE)
+    ) uart_rx_inst (
+        .clk           (clk),
+        .rst_p         (rst),
+        .rx_data       (uart_rx_data),
+        .rx_data_valid (uart_rx_data_valid),
+        .rx_data_ready (uart_rx_data_ready),
+        .rx_pin        (uart_rx)
+    );
+
+    // === Instanciation TX UART ===
+    uart_tx #(
+        .CLK_FRE(CLK_FRE),
+        .BAUD_RATE(UART_FRE)
+    ) uart_tx_inst (
+        .clk           (clk),
+        .rst_p         (rst),
+        .tx_data       (uart_tx_data),
+        .tx_data_valid (uart_tx_data_valid),
+        .tx_data_ready (uart_tx_data_ready),
+        .tx_pin        (uart_tx)
+    );
+
+endmodule