forked from tanchou/Verilog
96c234de6d
- Implemented rx_fifo module for receiving data with FIFO management. - Created tb_top_uart_rx_tx testbench for testing UART transmission and reception. - Developed tb_uart_rx testbench for validating UART receiver functionality. - Added tb_uart_tx testbench for testing UART transmitter behavior. - Designed top_led_uart module to interface UART with LED outputs. - Integrated top_uart_ultrasonic module for ultrasonic sensor data transmission via UART. - Implemented tx_fifo module for transmitting data with FIFO management. - Developed uart_rx module for receiving serial data with state machine control. - Created uart_top module to connect RX and TX functionalities with FIFO buffers. - Implemented uart_tx module for transmitting serial data with state machine control.
87 lines
2.2 KiB
Verilog
87 lines
2.2 KiB
Verilog
module uart_top(
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input wire clk,
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input wire rst,
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input wire uart_rx,
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output wire uart_tx,
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// Interfaces RX vers utilisateur
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output wire [7:0] rx_data,
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output wire rx_data_valid,
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input wire rx_data_ready,
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// Interfaces TX depuis utilisateur
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input wire [7:0] tx_data,
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input wire tx_data_valid,
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output wire tx_data_ready
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);
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parameter CLK_FRE = 27_000_000; // Hz
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parameter UART_FRE = 115200; // Baudrate
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// === Signaux internes ===
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wire [7:0] uart_rx_data;
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wire uart_rx_data_valid;
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wire uart_rx_data_ready;
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wire [7:0] uart_tx_data;
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wire uart_tx_data_valid;
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wire uart_tx_data_ready;
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// === FIFO RX ===
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rx_fifo #(
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.WIDTH(8),
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.DEPTH(16)
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) rx_fifo_inst (
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.clk (clk),
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.rst_p (rst),
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.rx_data_in (uart_rx_data),
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.rx_data_valid (uart_rx_data_valid),
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.rx_data_out (rx_data),
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.rx_data_ready (rx_data_ready),
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.fifo_empty (), // pas utilisé ici
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.fifo_full ()
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);
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// === FIFO TX ===
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tx_fifo #(
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.WIDTH(8),
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.DEPTH(16)
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) tx_fifo_inst (
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.clk (clk),
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.rst_p (rst),
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.tx_data_in (tx_data),
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.tx_data_valid (tx_data_valid),
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.tx_data_ready (tx_data_ready),
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.tx_data_out (uart_tx_data),
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.uart_tx_ready (uart_tx_data_ready)
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);
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// === Instanciation RX UART ===
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uart_rx #(
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.CLK_FRE(CLK_FRE),
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.BAUD_RATE(UART_FRE)
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) uart_rx_inst (
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.clk (clk),
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.rst_p (rst),
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.rx_data (uart_rx_data),
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.rx_data_valid (uart_rx_data_valid),
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.rx_data_ready (uart_rx_data_ready),
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.rx_pin (uart_rx)
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);
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// === Instanciation TX UART ===
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uart_tx #(
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.CLK_FRE(CLK_FRE),
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.BAUD_RATE(UART_FRE)
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) uart_tx_inst (
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.clk (clk),
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.rst_p (rst),
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.tx_data (uart_tx_data),
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.tx_data_valid (uart_tx_data_valid),
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.tx_data_ready (uart_tx_data_ready),
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.tx_pin (uart_tx)
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);
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endmodule
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