forked from tanchou/Verilog
loopback fonctionne avec le rxuartlite
This commit is contained in:
@@ -52,7 +52,7 @@ module rxuartlite #(
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`ifdef FORMAL
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`ifdef FORMAL
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parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, // Necessary for formal proof
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parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, // Necessary for formal proof
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`else
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`else
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parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 868, // 115200 Baud at 100MHz
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parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 234, // 115200 Baud at 100MHz
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`endif
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`endif
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localparam TB = TIMER_BITS,
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localparam TB = TIMER_BITS,
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//
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//
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@@ -19,7 +19,7 @@ if not exist runs (
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)
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)
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echo === Étape 1 : Synthèse avec Yosys ===
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echo === Étape 1 : Synthèse avec Yosys ===
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yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/other_rx.v IP/verilog/rxuartlite.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
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yosys -p "read_verilog -sv src/verilog/%TOP%1.v IP/verilog/other_rx.v IP/verilog/rxuartlite.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
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if errorlevel 1 goto error
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if errorlevel 1 goto error
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echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===
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echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===
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@@ -27,6 +27,14 @@ module top_uart_loopback (
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.rx_data(rx_data)
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.rx_data(rx_data)
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);*/
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);*/
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rxuartlite uart_rx_inst (
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.i_clk(clk),
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.i_reset(1'b0),
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.i_uart_rx(rx),
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.o_wr(rx_received),
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.o_data(rx_data)
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);
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reg [7:0] stored_data;
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reg [7:0] stored_data;
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reg [7:0] data_const = 8'h31;
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reg [7:0] data_const = 8'h31;
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@@ -38,7 +46,7 @@ wire r;
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uart_tx uart_tx_inst (
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uart_tx uart_tx_inst (
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.clk(clk),
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.clk(clk),
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.rst_p(1'b0),
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.rst_p(1'b0),
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.data(data_const),
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.data(tx_data),
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.tx_enable(tx_enable),
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.tx_enable(tx_enable),
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.tx_ready(tx_ready),
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.tx_ready(tx_ready),
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.tx(tx)
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.tx(tx)
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@@ -115,6 +123,10 @@ localparam DATA_BYTE = 8'h31; // ASCII '1'
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// Start new transmission
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// Start new transmission
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tx_enable <= 1'b1;
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tx_enable <= 1'b1;
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data_const <= DATA_BYTE;
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data_const <= DATA_BYTE;
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tx_data <= rx_data;
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//leds[5:0] <= rx_data[5:0]; // Display received data on LEDs
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leds[5] <= rx_received;
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delay_counter <= DELAY_CYCLES;
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delay_counter <= DELAY_CYCLES;
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end
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end
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else if (delay_counter > 0) begin
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else if (delay_counter > 0) begin
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