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loopback fonctionne avec le rxuartlite

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This commit is contained in:
Gamenight77
2025-05-09 09:15:28 +02:00
parent 93e0e96798
commit a792f85adf
3 changed files with 16 additions and 4 deletions
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2
Semaine_4/UART/IP/verilog/rxuartlite.v
View File

@@ -52,7 +52,7 @@ module rxuartlite #(
`ifdef FORMAL
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, // Necessary for formal proof
`else
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 868, // 115200 Baud at 100MHz
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 234, // 115200 Baud at 100MHz
`endif
localparam TB = TIMER_BITS,
//

2
Semaine_4/UART/scripts/build.bat
View File

@@ -19,7 +19,7 @@ if not exist runs (
)
echo === Étape 1 : Synthèse avec Yosys ===
yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/other_rx.v IP/verilog/rxuartlite.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
yosys -p "read_verilog -sv src/verilog/%TOP%1.v IP/verilog/other_rx.v IP/verilog/rxuartlite.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
if errorlevel 1 goto error
echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===

14
Semaine_4/UART/src/verilog/top_uart_loopback1.v
View File

@@ -27,6 +27,14 @@ module top_uart_loopback (
.rx_data(rx_data)
);*/
rxuartlite uart_rx_inst (
.i_clk(clk),
.i_reset(1'b0),
.i_uart_rx(rx),
.o_wr(rx_received),
.o_data(rx_data)
);
reg [7:0] stored_data;
reg [7:0] data_const = 8'h31;
@@ -38,7 +46,7 @@ wire r;
uart_tx uart_tx_inst (
.clk(clk),
.rst_p(1'b0),
.data(data_const),
.data(tx_data),
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.tx(tx)
@@ -115,6 +123,10 @@ localparam DATA_BYTE = 8'h31; // ASCII '1'
// Start new transmission
tx_enable <= 1'b1;
data_const <= DATA_BYTE;
tx_data <= rx_data;
//leds[5:0] <= rx_data[5:0]; // Display received data on LEDs
leds[5] <= rx_received;
delay_counter <= DELAY_CYCLES;
end
else if (delay_counter > 0) begin