First simulation

Introduction/counter/dump.vcd

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+$date
+	Sat Mar 22 10:16:37 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module tb_counter $end
+$scope module counter_inst $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$var reg 4 # count [3:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+bx #
+0"
+0!
+$end
+#5
+0!
+#10
+0!
+#15
+0!
+#20
+b0 #
+0!
+1"
+#25
+0!
+#30
+0!
+#35
+0!
+#40
+0!
+#45
+0!
+#50
+0!
+#55
+0!
+#60
+0!
+#65
+0!
+#70
+0!
+#75
+0!
+#80
+0!
+#85
+0!
+#90
+0!
+#95
+0!
+#100
+b1 #
+0!
+0"
+#105
+b10 #
+0!
+#110
+b11 #
+0!
+#115
+b100 #
+0!
+#120
+b101 #
+0!
+#125
+b110 #
+0!
+#130
+b111 #
+0!
+#135
+b1000 #
+0!
+#140
+b1001 #
+0!
+#145
+b1010 #
+0!
+#150
+b0 #
+0!
+1"
+#155
+0!
+#160
+0!
+#165
+0!
+#170
+0!