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Louis TANCHOU e651a94dbe First simulation
2025-03-22 10:19:11 +01:00
Introduction/counter
First simulation
2025-03-22 10:19:11 +01:00
README.md
Initial commit
2025-03-22 09:16:50 +01:00

README.md

Verilog

Description
No description provided
Readme 218 MiB
Languages
Verilog 75.7%
Tcl 9.8%
Batchfile 5%
Shell 3.5%
Python 3.1%
Other 2.8%