forked from tanchou/Verilog
First simulation
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@@ -12,7 +12,9 @@ module tb_counter;
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always #5 clk = ~clk;
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initial begin
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$dumpfile("dump.vcd"); // Nom du fichier de traces
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$dumpvars(0, counter_inst);
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clk <= 0;
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rst <= 0;
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