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forked from tanchou/Verilog

First simulation

This commit is contained in:
2025-03-22 10:19:11 +01:00
parent 2c08e4bbbe
commit e651a94dbe
3 changed files with 194 additions and 1 deletions

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@@ -12,7 +12,9 @@ module tb_counter;
always #5 clk = ~clk;
initial begin
$dumpfile("dump.vcd"); // Nom du fichier de traces
$dumpvars(0, counter_inst);
clk <= 0;
rst <= 0;