First simulation

Introduction/counter/counter_tb.out

@@ -0,0 +1,82 @@
+#! /etc/oss-cad-suite/bin/vvp
+:ivl_version "13.0 (devel)" "(s20250103-26-gb0c57ab17)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/etc/oss-cad-suite/lib/ivl/system.vpi";
+:vpi_module "/etc/oss-cad-suite/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/etc/oss-cad-suite/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/etc/oss-cad-suite/lib/ivl/v2005_math.vpi";
+:vpi_module "/etc/oss-cad-suite/lib/ivl/va_math.vpi";
+S_0x55556626c580 .scope module, "tb_counter" "tb_counter" 2 1;
+ .timescale 0 0;
+v0x55556627e4a0_0 .var "clk", 0 0;
+v0x55556627e570_0 .net "count", 3 0, v0x55556627e2a0_0;  1 drivers
+v0x55556627e640_0 .var "rst", 0 0;
+S_0x55556626c710 .scope module, "counter_inst" "counter" 2 6, 3 1 0, S_0x55556626c580;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /OUTPUT 4 "count";
+v0x555566232d40_0 .net "clk", 0 0, v0x55556627e4a0_0;  1 drivers
+v0x55556627e2a0_0 .var "count", 3 0;
+v0x55556627e380_0 .net "rst", 0 0, v0x55556627e640_0;  1 drivers
+E_0x555566233390 .event posedge, v0x555566232d40_0;
+    .scope S_0x55556626c710;
+T_0 ;
+    %wait E_0x555566233390;
+    %load/vec4 v0x55556627e380_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.0, 8;
+    %pushi/vec4 0, 0, 4;
+    %assign/vec4 v0x55556627e2a0_0, 0;
+    %jmp T_0.1;
+T_0.0 ;
+    %load/vec4 v0x55556627e2a0_0;
+    %addi 1, 0, 4;
+    %assign/vec4 v0x55556627e2a0_0, 0;
+T_0.1 ;
+    %jmp T_0;
+    .thread T_0;
+    .scope S_0x55556626c580;
+T_1 ;
+    %delay 5, 0;
+    %load/vec4 v0x55556627e4a0_0;
+    %inv;
+    %store/vec4 v0x55556627e4a0_0, 0, 1;
+    %jmp T_1;
+    .thread T_1;
+    .scope S_0x55556626c580;
+T_2 ;
+    %vpi_call 2 15 "$dumpfile", "dump.vcd" {0 0 0};
+    %vpi_call 2 16 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x55556626c710 {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x55556627e4a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x55556627e640_0, 0;
+    %delay 20, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55556627e640_0, 0, 1;
+    %delay 80, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55556627e640_0, 0, 1;
+    %delay 50, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55556627e640_0, 0, 1;
+    %delay 20, 0;
+    %vpi_call 2 26 "$finish" {0 0 0};
+    %end;
+    .thread T_2;
+    .scope S_0x55556626c580;
+T_3 ;
+    %delay 5, 0;
+    %load/vec4 v0x55556627e4a0_0;
+    %inv;
+    %store/vec4 v0x55556627e4a0_0, 0, 1;
+    %jmp T_3;
+    .thread T_3;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "tb_counter.v";
+    "counter.v";

Introduction/counter/dump.vcd

@@ -0,0 +1,109 @@
+$date
+	Sat Mar 22 10:16:37 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module tb_counter $end
+$scope module counter_inst $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$var reg 4 # count [3:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+bx #
+0"
+0!
+$end
+#5
+0!
+#10
+0!
+#15
+0!
+#20
+b0 #
+0!
+1"
+#25
+0!
+#30
+0!
+#35
+0!
+#40
+0!
+#45
+0!
+#50
+0!
+#55
+0!
+#60
+0!
+#65
+0!
+#70
+0!
+#75
+0!
+#80
+0!
+#85
+0!
+#90
+0!
+#95
+0!
+#100
+b1 #
+0!
+0"
+#105
+b10 #
+0!
+#110
+b11 #
+0!
+#115
+b100 #
+0!
+#120
+b101 #
+0!
+#125
+b110 #
+0!
+#130
+b111 #
+0!
+#135
+b1000 #
+0!
+#140
+b1001 #
+0!
+#145
+b1010 #
+0!
+#150
+b0 #
+0!
+1"
+#155
+0!
+#160
+0!
+#165
+0!
+#170
+0!

Introduction/counter/tb_counter.v

@@ -12,7 +12,9 @@ module tb_counter;
     always #5 clk = ~clk;
     
     initial begin
-        
+        $dumpfile("dump.vcd");  // Nom du fichier de traces
+        $dumpvars(0, counter_inst);  
+
         clk <= 0;
         rst <= 0;