3 Commits

Author	SHA1	Message	Date
Gamenight77	5f3568ff9b	Enhance ultrasonic_fpga module: add comment to clarify FSM behavior in the Verilog file	2025-04-22 14:40:12 +02:00
Gamenight77	2be0cb20f6	Refactor ultrasonic_fpga module: improve code readability by adjusting comments and formatting in the Verilog file.	2025-04-22 14:38:50 +02:00
Gamenight77	3bb56e2f57	Init et début de réflexion sur le projet	2025-04-22 09:56:06 +02:00