verlan/Verilog_Louis
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Code Pull Requests Activity
53 Commits 1 Branch 0 Tags
86d4f5ddd2f355ecd99ae9d5959e4bb2ae7fa651
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3 Commits

Author SHA1 Message Date
Gamenight77
1ca3456ab8 Création de la structure du uart fifo 2025-05-06 09:42:26 +02:00
Gamenight77
e0a54fb42a Add LED indication for RX signal in top_uart_loopback module 2025-05-05 14:54:40 +02:00
Gamenight77
589c36ed83 Loopback ne fonctionne pas 2025-05-05 14:52:01 +02:00