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forked from tanchou/Verilog
Commit Graph

13 Commits

Author SHA1 Message Date
Gamenight77
a162a2a1bb Update LED display logic to show received data instead of received signal 2025-05-09 09:15:44 +02:00
Gamenight77
a792f85adf loopback fonctionne avec le rxuartlite 2025-05-09 09:15:28 +02:00
Gamenight77
6bb42700f8 Update TX data assignment in UART loopback module to send fixed value 2025-05-07 18:05:02 +02:00
Gamenight77
f990a6f6d3 Fix UART RX module instantiation and update build script for correct file references 2025-05-07 11:07:42 +02:00
Gamenight77
83c40bee28 Fix build script and update state machine in UART loopback module 2025-05-07 10:39:52 +02:00
Gamenight77
abef18227c Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality 2025-05-07 09:46:43 +02:00
Gamenight77
1ca3456ab8 Création de la structure du uart fifo 2025-05-06 09:42:26 +02:00
Gamenight77
e0a54fb42a Add LED indication for RX signal in top_uart_loopback module 2025-05-05 14:54:40 +02:00
Gamenight77
589c36ed83 Loopback ne fonctionne pas 2025-05-05 14:52:01 +02:00
Gamenight77
87732dcf87 uart modules work 2025-05-05 09:58:19 +02:00
Gamenight77
fc48941459 uart_rx valid 2025-05-05 09:51:23 +02:00
Gamenight77
c9a5fba97e TX tested with other's rx code (its work) 2025-05-05 09:26:41 +02:00
Gamenight77
f5e73d7379 struct 2025-05-02 15:51:18 +02:00