forked from tanchou/Verilog
7a2fbc0195
- Created a new testbench file `top_ultrasonic_led_tb.vvp` to simulate the `top_ultrasonic_led` module. - Defined the necessary signals and events for testing the ultrasonic sensor functionality. - Implemented the main test sequence including triggering the ultrasonic sensor and monitoring the output LEDs based on distance measurements. - Included timing and state management for accurate simulation of the ultrasonic sensor behavior.
28 lines
658 B
Verilog
28 lines
658 B
Verilog
module top_ultrasonic_led (
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input wire clk,
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input wire rst,
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input wire start, // bouton ou signal de départ
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input wire echo, // signal du capteur
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output wire trig, // vers le capteur
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output wire [5:0] leds // sorties LED
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);
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wire [8:0] distance;
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// Module de mesure de distance
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ultrasonic_fpga ultrasonic_inst (
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.clk(clk),
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.rst(rst),
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.start(start),
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.echo(echo),
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.trig_out(trig),
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.distance(distance)
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);
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// Module d'affichage leds
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distance_display_led led_display_inst (
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.distance(distance),
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.leds(leds)
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);
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endmodule |