forked from tanchou/Verilog
66fa5b2650
- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs. - Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.
13 lines
183 B
Verilog
13 lines
183 B
Verilog
module top (
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input wire clk,
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input wire btn1,
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output wire [3:0] count
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);
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counter uut (
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.clk(clk),
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.btn1(btn1),
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.count(count)
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);
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endmodule |