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Gamenight77 96c234de6d Add UART communication modules and testbenches 
- Implemented rx_fifo module for receiving data with FIFO management.
- Created tb_top_uart_rx_tx testbench for testing UART transmission and reception.
- Developed tb_uart_rx testbench for validating UART receiver functionality.
- Added tb_uart_tx testbench for testing UART transmitter behavior.
- Designed top_led_uart module to interface UART with LED outputs.
- Integrated top_uart_ultrasonic module for ultrasonic sensor data transmission via UART.
- Implemented tx_fifo module for transmitting data with FIFO management.
- Developed uart_rx module for receiving serial data with state machine control.
- Created uart_top module to connect RX and TX functionalities with FIFO buffers.
- Implemented uart_tx module for transmitting serial data with state machine control.
2025-04-28 17:13:39 +02:00
..
Capteur_recule_bidirectionel_V2
Refactor ws2812_driver module for improved timing and data handling
2025-04-28 14:30:29 +02:00
Projet_esp32
New Week
2025-04-28 09:22:17 +02:00
UARTV2
Add UART communication modules and testbenches
2025-04-28 17:13:39 +02:00
README.md
New Week
2025-04-28 09:22:17 +02:00

README.md

Semaine 2

Jour 6

Matin :

  • Remise en contexte
  • Réflexion sur un projet combinant FPGA (Tang Nano 20K) + ESP32 :
    • Objectif : se connecter à l’ESP32 (Wi-Fi) → communiquer avec le PC (via USB au FPGA)
    • L’ESP32 agit comme un esclave, servant uniquement de portail Wi-Fi
    • Le FPGA fait le lien entre Wi-Fi et périphériques USB

Architecture prévue : [ PC via USB-C ] ←→ [ FPGA (Tang Nano 20K) ] ←→ [ ESP32 ] ←→ [ Clients en Wi-Fi ]

Après-midi :

  • Documentation sur l’esp 32