forked from tanchou/Verilog
96c234de6d
- Implemented rx_fifo module for receiving data with FIFO management. - Created tb_top_uart_rx_tx testbench for testing UART transmission and reception. - Developed tb_uart_rx testbench for validating UART receiver functionality. - Added tb_uart_tx testbench for testing UART transmitter behavior. - Designed top_led_uart module to interface UART with LED outputs. - Integrated top_uart_ultrasonic module for ultrasonic sensor data transmission via UART. - Implemented tx_fifo module for transmitting data with FIFO management. - Developed uart_rx module for receiving serial data with state machine control. - Created uart_top module to connect RX and TX functionalities with FIFO buffers. - Implemented uart_tx module for transmitting serial data with state machine control.
50 lines
1.6 KiB
Verilog
50 lines
1.6 KiB
Verilog
module rx_fifo #(
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parameter WIDTH = 8, // Taille des données (8 bits)
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parameter DEPTH = 16 // Taille de la FIFO
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)(
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input clk,
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input rst_p,
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input [WIDTH-1:0] rx_data_in,
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input rx_data_valid, // Indique que les données reçues sont valides
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output reg [WIDTH-1:0] rx_data_out,
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output reg rx_data_ready, // Indique que les données peuvent être lues
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output reg fifo_empty, // FIFO vide
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output reg fifo_full // FIFO pleine
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);
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reg [WIDTH-1:0] fifo_mem [DEPTH-1:0]; // Mémoire FIFO
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reg [4:0] wr_ptr = 0; // Pointeur d'écriture
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reg [4:0] rd_ptr = 0; // Pointeur de lecture
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reg [4:0] fifo_count = 0; // Compteur d'éléments dans la FIFO
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always @(posedge clk or posedge rst_p) begin
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if (rst_p) begin
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wr_ptr <= 0;
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rd_ptr <= 0;
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fifo_count <= 0;
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rx_data_ready <= 0;
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fifo_empty <= 1;
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fifo_full <= 0;
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end else begin
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// Écriture dans la FIFO
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if (rx_data_valid && !fifo_full) begin
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fifo_mem[wr_ptr] <= rx_data_in;
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wr_ptr <= wr_ptr + 1;
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fifo_count <= fifo_count + 1;
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end
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// Lecture de la FIFO
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if (!fifo_empty) begin
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rx_data_out <= fifo_mem[rd_ptr];
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rd_ptr <= rd_ptr + 1;
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fifo_count <= fifo_count - 1;
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end
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// Mise à jour des indicateurs de vide et de plein
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fifo_empty <= (fifo_count == 0);
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fifo_full <= (fifo_count == DEPTH);
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rx_data_ready <= !fifo_empty;
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end
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end
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endmodule
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