forked from tanchou/Verilog
96c234de6d
- Implemented rx_fifo module for receiving data with FIFO management. - Created tb_top_uart_rx_tx testbench for testing UART transmission and reception. - Developed tb_uart_rx testbench for validating UART receiver functionality. - Added tb_uart_tx testbench for testing UART transmitter behavior. - Designed top_led_uart module to interface UART with LED outputs. - Integrated top_uart_ultrasonic module for ultrasonic sensor data transmission via UART. - Implemented tx_fifo module for transmitting data with FIFO management. - Developed uart_rx module for receiving serial data with state machine control. - Created uart_top module to connect RX and TX functionalities with FIFO buffers. - Implemented uart_tx module for transmitting serial data with state machine control.
62 lines
1.3 KiB
Verilog
62 lines
1.3 KiB
Verilog
module top_led_uart(
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input wire clk,
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input wire rx,
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output wire tx,
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output reg [5:0] leds
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);
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wire [7:0] data_out;
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wire valid;
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reg start_tx = 0;
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reg [7:0] data_in = 0;
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uart_top uart (
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.clk(clk),
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.start(start_tx),
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.data_in(data_in),
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.rx(rx),
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.data_out(data_out),
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.valid(valid),
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.tx(tx)
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);
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reg [1:0] state = 0;
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localparam IDLE = 2'd0;
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localparam TOGGLE = 2'd1;
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localparam SEND_BACK = 2'd2;
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always @(posedge clk) begin
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case (state)
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INIT: begin
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leds <= 6'b000000;
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start_tx <= 0;
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if (valid) begin
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leds <= data_out[5:0];
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state <= SEND_BACK;
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end
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end
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IDLE: begin
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start_tx <= 0;
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if (valid) begin
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leds <= data_out[5:0];
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state <= SEND_BACK;
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end
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end
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SEND_BACK: begin
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data_in <= data_out;
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start_tx <= 1;
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state <= TOGGLE;
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end
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TOGGLE: begin
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start_tx <= 0;
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state <= IDLE;
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end
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endcase
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end
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endmodule
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