forked from tanchou/Verilog
96c234de6d
- Implemented rx_fifo module for receiving data with FIFO management. - Created tb_top_uart_rx_tx testbench for testing UART transmission and reception. - Developed tb_uart_rx testbench for validating UART receiver functionality. - Added tb_uart_tx testbench for testing UART transmitter behavior. - Designed top_led_uart module to interface UART with LED outputs. - Integrated top_uart_ultrasonic module for ultrasonic sensor data transmission via UART. - Implemented tx_fifo module for transmitting data with FIFO management. - Developed uart_rx module for receiving serial data with state machine control. - Created uart_top module to connect RX and TX functionalities with FIFO buffers. - Implemented uart_tx module for transmitting serial data with state machine control.
134 lines
3.7 KiB
Verilog
134 lines
3.7 KiB
Verilog
module top_uart_ultrasonic (
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input wire clk,
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input wire rst_p,
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input wire start, // Démarrage de la mesure
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inout wire sig, // Signal vers le capteur ultrason
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output wire uart_tx // TX vers le PC
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);
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wire [15:0] distance;
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wire [2:0] state;
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reg [7:0] tx_data_in;
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reg tx_data_valid;
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wire tx_data_ready;
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wire fifo_empty;
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wire fifo_full;
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wire uart_ready;
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reg uart_start;
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reg [7:0] uart_data;
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reg [1:0] send_state;
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localparam IDLE = 2'd0,
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SEND_HIGH = 2'd1,
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SEND_LOW = 2'd2,
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WAIT_UART = 2'd3;
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// Instanciation du module ultrason
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ultrasonic_fpga #(
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.CLK_FREQ(27_000_000)
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) ultrasonic_inst (
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.clk(clk),
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.start(start),
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.sig(sig),
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.distance(distance),
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.state(state)
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);
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// Instanciation de la FIFO
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tx_fifo #(
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.WIDTH(8),
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.DEPTH(16)
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) fifo_inst (
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.clk(clk),
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.rst_p(rst_p),
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.tx_data_in(tx_data_in),
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.tx_data_valid(tx_data_valid),
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.tx_data_ready(tx_data_ready),
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.fifo_empty(fifo_empty),
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.fifo_full(fifo_full)
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);
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// Instanciation de l'UART
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uart_tx uart_inst (
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.clk(clk),
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.rst(rst_p),
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.tx_start(uart_start),
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.tx_data(uart_data),
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.tx(uart_tx),
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.tx_ready(uart_ready)
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);
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reg [15:0] distance_reg;
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reg new_distance;
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// Détecte un nouveau résultat de distance
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always @(posedge clk or posedge rst_p) begin
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if (rst_p) begin
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distance_reg <= 16'd0;
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new_distance <= 1'b0;
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end else begin
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if (state == 3'd6 && distance != distance_reg) begin // Quand l'ultrason est à DONE
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distance_reg <= distance;
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new_distance <= 1'b1;
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end else begin
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new_distance <= 1'b0;
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end
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end
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end
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// Envoi dans la FIFO (distance sur 2 octets : high byte + low byte)
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always @(posedge clk or posedge rst_p) begin
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if (rst_p) begin
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tx_data_in <= 8'd0;
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tx_data_valid <= 1'b0;
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send_state <= IDLE;
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end else begin
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case (send_state)
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IDLE: begin
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tx_data_valid <= 1'b0;
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if (new_distance && !fifo_full) begin
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tx_data_in <= distance_reg[15:8]; // MSB en premier
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tx_data_valid <= 1'b1;
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send_state <= SEND_LOW;
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end
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end
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SEND_LOW: begin
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tx_data_valid <= 1'b0;
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if (tx_data_ready && !fifo_full) begin
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tx_data_in <= distance_reg[7:0]; // LSB ensuite
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tx_data_valid <= 1'b1;
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send_state <= WAIT_UART;
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end
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end
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WAIT_UART: begin
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tx_data_valid <= 1'b0;
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send_state <= IDLE;
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end
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default: send_state <= IDLE;
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endcase
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end
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end
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// Gestion FIFO -> UART
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always @(posedge clk or posedge rst_p) begin
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if (rst_p) begin
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uart_start <= 1'b0;
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uart_data <= 8'd0;
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end else begin
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uart_start <= 1'b0; // Par défaut
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if (uart_ready && !fifo_empty) begin
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uart_data <= fifo_inst.fifo_mem[fifo_inst.rd_ptr]; // Lecture de la FIFO
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uart_start <= 1'b1;
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fifo_inst.rd_ptr <= fifo_inst.rd_ptr + 1;
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fifo_inst.fifo_count <= fifo_inst.fifo_count - 1;
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end
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end
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end
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endmodule
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