forked from tanchou/Verilog
- Implemented rx_fifo module for receiving data with FIFO management. - Created tb_top_uart_rx_tx testbench for testing UART transmission and reception. - Developed tb_uart_rx testbench for validating UART receiver functionality. - Added tb_uart_tx testbench for testing UART transmitter behavior. - Designed top_led_uart module to interface UART with LED outputs. - Integrated top_uart_ultrasonic module for ultrasonic sensor data transmission via UART. - Implemented tx_fifo module for transmitting data with FIFO management. - Developed uart_rx module for receiving serial data with state machine control. - Created uart_top module to connect RX and TX functionalities with FIFO buffers. - Implemented uart_tx module for transmitting serial data with state machine control.
58 lines
1.7 KiB
Verilog
58 lines
1.7 KiB
Verilog
module tx_fifo #(
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parameter WIDTH = 8, // Taille des données (8 bits)
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parameter DEPTH = 16 // Taille de la FIFO
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)(
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input wire clk,
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input wire rst_p,
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// Entrée utilisateur
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input wire [WIDTH-1:0] tx_data_in,
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input wire tx_data_valid, // Donnée disponible à écrire
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output wire tx_data_ready, // FIFO prête à recevoir
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// Sortie vers UART
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output reg [WIDTH-1:0] tx_data_out,
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input wire uart_tx_ready, // UART demande une donnée
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output reg fifo_empty,
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output reg fifo_full
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);
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reg [WIDTH-1:0] fifo_mem [DEPTH-1:0];
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reg [4:0] wr_ptr = 0;
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reg [4:0] rd_ptr = 0;
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reg [4:0] fifo_count = 0;
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always @(posedge clk or posedge rst_p) begin
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if (rst_p) begin
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wr_ptr <= 0;
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rd_ptr <= 0;
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fifo_count <= 0;
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fifo_empty <= 1;
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fifo_full <= 0;
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tx_data_out <= 0;
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end else begin
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// Écriture dans FIFO
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if (tx_data_valid && !fifo_full) begin
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fifo_mem[wr_ptr] <= tx_data_in;
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wr_ptr <= wr_ptr + 1;
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fifo_count <= fifo_count + 1;
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end
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// Lecture depuis FIFO
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if (uart_tx_ready && !fifo_empty) begin
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tx_data_out <= fifo_mem[rd_ptr];
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rd_ptr <= rd_ptr + 1;
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fifo_count <= fifo_count - 1;
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end
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// Mise à jour des flags
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fifo_empty <= (fifo_count == 0);
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fifo_full <= (fifo_count == DEPTH);
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end
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end
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// FIFO est prête à recevoir des données si pas pleine
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assign tx_data_ready = !fifo_full;
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endmodule
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