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Verilog_Louis
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e086ba8ef0d87887fe9a3cc31c8162260de993b1
Verilog_Louis
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Semaine_4
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UART_FIFO
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tests
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Python
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Gamenight77
1ca3456ab8
Création de la structure du uart fifo
2025-05-06 09:42:26 +02:00
..
uart_loopback_test.py
Création de la structure du uart fifo
2025-05-06 09:42:26 +02:00