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Verilog_Louis/Semaine_4/UART/src/verilog/top_uart_loopback.v

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module top_uart_loopback (
input wire clk, // 27 MHz
input wire rx,
output wire tx,
output reg [5:0] leds
);
wire rx_received;
wire [7:0] rx_data;
reg [7:0] tx_data;
reg tx_enable;
wire tx_ready;
initial begin
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leds = 6'b111111;
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end
// === UART RX ===
uart_rx uart_rx_inst (
.clk(clk),
.rst_p(1'b0),
.rx_pin(rx),
.rx_received(rx_received),
.rx_enable(1'b1),
.rx_data(rx_data)
);
// === UART TX ===
uart_tx uart_tx_inst (
.clk(clk),
.rst_p(1'b0),
.data(tx_data),
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.tx(tx)
);
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// === FSM avec délai ===
localparam IDLE = 0, WAIT = 1, SEND = 2;
reg [1:0] state = IDLE;
reg [8:0] delay_counter = 0;
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always @(posedge clk) begin
leds[5] <= rx;
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leds[4] <= tx;
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case (state)
IDLE: begin
tx_enable <= 0;
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delay_counter <= 0;
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if (rx_received && tx_ready) begin
tx_data <= rx_data;
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state <= WAIT;
leds[0] <= 0;
leds[1] <= 1;
end
end
WAIT: begin
delay_counter <= delay_counter + 1;
if (delay_counter == 8'd400 && tx_ready) begin
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tx_enable <= 1;
state <= SEND;
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end else begin
tx_enable <= 0;
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end
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leds[0] <= 1;
leds[1] <= 0;
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end
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SEND: begin
tx_enable <= 0;
state <= IDLE;
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leds[0] <= 0;
leds[1] <= 0; // Envoi terminé
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end
endcase
end
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endmodule