forked from tanchou/Verilog
Refactor distance data type from 15 bits to 9 bits in ultrasonic_fpga module and update related testbench for consistency
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@@ -6,7 +6,7 @@ module ultrasonic_fpga #(
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input wire start, // signal de declenchement
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input wire echo, // retour du capteur
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output reg trig_out, // signal envoye au capteur
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output reg [15:0] distance // distance mesuree
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output reg [8:0] distance // distance mesuree
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);
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reg [2:0] state;
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