Add DHT11 UART communication module and related components

- Implemented a FIFO buffer in Verilog for data storage.
- Created a simplified UART transmitter (txuartlite) for serial communication.
- Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow.
- Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission.
- Added a testbench (tb_dht11) for simulating the DHT11 module functionality.
- Updated README with project description and command references.
- Created build and simulation scripts for both Linux and Windows environments.
- Added constraints file for hardware configuration.
- Implemented a state machine for managing measurement and data transmission.

Semaine_6/DHT11_UART/scripts/linux/build.sh

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+#!/bin/bash
+
+# Aller à la racine du projet
+cd "$(dirname "$0")/../.." || exit 1
+
+# Config de base
+DEVICE="GW2AR-LV18QN88C8/I7"
+BOARD="tangnano20k"
+TOP="dht11_uart_top"
+CST_FILE="$TOP.cst"
+JSON_FILE="runs/$TOP.json"
+PNR_JSON="runs/pnr_$TOP.json"
+BITSTREAM="runs/$TOP.fs"
+
+# Créer le dossier runs si nécessaire
+mkdir -p runs
+
+echo "=== Étape 1 : Synthèse avec Yosys ==="
+yosys -p "read_verilog -sv src/verilog/$TOP.v IP/verilog/dht11_interface.v IP/verilog/uart_tx_fifo.v  IP/verilog/fifo.v IP/verilog/txuartlite.v; synth_gowin -top $TOP -json $JSON_FILE"
+if [ $? -ne 0 ]; then
+  echo "=== Erreur lors de la synthèse ==="
+  exit 1
+fi
+
+echo "=== Étape 2 : Placement & Routage avec nextpnr-himbaechel ==="
+nextpnr-himbaechel --json "$JSON_FILE" --write "$PNR_JSON" --device "$DEVICE" --vopt cst=constraints/"$CST_FILE" --vopt family=GW2A-18C
+if [ $? -ne 0 ]; then
+  echo "=== Erreur lors du placement/routage ==="
+  exit 1
+fi
+
+echo "=== Étape 3 : Packing avec gowin_pack ==="
+gowin_pack -d "$DEVICE" -o "$BITSTREAM" "$PNR_JSON"
+if [ $? -ne 0 ]; then
+  echo "=== Erreur lors du packing ==="
+  exit 1
+fi
+
+echo "=== Étape 4 : Flash avec openFPGALoader ==="
+openFPGALoader -b "$BOARD" "$BITSTREAM"
+if [ $? -ne 0 ]; then
+  echo "=== Erreur lors du flash ==="
+  exit 1
+fi
+
+echo "=== Compilation et flash réussis ==="

Semaine_6/DHT11_UART/scripts/linux/clean.sh

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+#!/bin/bash
+
+echo "=== Nettoyage des fichiers générés ==="
+rm -rf runs/*

Semaine_6/DHT11_UART/scripts/linux/gtkwave.sh

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+#!/bin/bash
+
+echo "=== Lancement de GTKWave ==="
+gtkwave runs/sim.vcd
+echo "=== GTKWave terminé ==="

Semaine_6/DHT11_UART/scripts/linux/simulate.sh

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+#!/bin/bash
+
+echo "=== Simulation avec Icarus Verilog ==="
+
+OUT="runs/sim.vvp"
+TOP="tb_dht11"
+DIRS=("src/verilog" "tests/verilog")
+
+FILES=()
+for dir in "${DIRS[@]}"; do
+  for file in "$dir"/*.v; do
+    FILES+=("$file")
+  done
+done
+
+iverilog -g2012 -o "$OUT" -s "$TOP" "${FILES[@]}"
+vvp "$OUT"