forked from tanchou/Verilog
Add UART TX module and testbench, update scripts and constraints
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19
Semaine_4/FIFO/tests/verilog/tb_fifo.v
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19
Semaine_4/FIFO/tests/verilog/tb_fifo.v
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`timescale 1ns/1ps
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module tb_fifo;
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reg clk = 0;
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always #18.5 clk = ~clk;
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initial begin
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$dumpfile("runs/fifo.vcd");
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$dumpvars(0, tb_fifo);
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end
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endmodule
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