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forked from tanchou/Verilog

Add UART TX module and testbench, update scripts and constraints

This commit is contained in:
Gamenight77
2025-05-05 15:23:44 +02:00
parent e0a54fb42a
commit 7156abf4e7
9 changed files with 145 additions and 0 deletions

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`timescale 1ns/1ps
module tb_fifo;
reg clk = 0;
always #18.5 clk = ~clk;
initial begin
$dumpfile("runs/fifo.vcd");
$dumpvars(0, tb_fifo);
end
endmodule