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forked from tanchou/Verilog

Add testbench for top_ultrasonic_led module

- Created a new testbench file `top_ultrasonic_led_tb.vvp` to simulate the `top_ultrasonic_led` module.
- Defined the necessary signals and events for testing the ultrasonic sensor functionality.
- Implemented the main test sequence including triggering the ultrasonic sensor and monitoring the output LEDs based on distance measurements.
- Included timing and state management for accurate simulation of the ultrasonic sensor behavior.
This commit is contained in:
Gamenight77
2025-04-16 14:23:18 +02:00
parent 079159bdb8
commit 7a2fbc0195
12 changed files with 8335 additions and 0 deletions

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`timescale 1ns/1ps
module tb_top_ultrasonic_led;
reg clk;
reg rst;
reg start;
reg echo;
wire trig;
wire [5:0] leds;
// Instance du module top
top_ultrasonic_led uut (
.clk(clk),
.rst(rst),
.start(start),
.echo(echo),
.trig(trig),
.leds(leds)
);
always #18.5 clk = ~clk;
initial begin
// Initialisation
$dumpfile("top_ultrasonic_led.vcd");
$dumpvars(0, tb_top_ultrasonic_led);
clk = 0;
rst = 1;
start = 0;
echo = 0;
#100;
rst = 0;
#50;
start = 1;
#20;
start = 0;
// Attente du signal trig
wait (trig == 1);
$display("TRIG HIGH at %t", $time);
wait (trig == 0);
$display("TRIG LOW at %t", $time);
repeat (500) @(posedge clk);
echo = 1;
#12000
echo = 0;
repeat (500) @(posedge clk);
$display("Leds allumer : %b", leds);
$finish;
end
endmodule