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Fix clock period comment in testbench for clarity

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Gamenight77
2025-04-16 13:32:08 +02:00
parent c8f108e01d
commit a00122b595
1 changed files with 1 additions and 1 deletions
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Semaine 1/Ultrasonic/tb_ultrasonic_fpga.v
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@@ -11,7 +11,7 @@ module tb_ultrasonic_fpga;
time t_start, t_end; time t_start, t_end;
// Clock 27MHz => periode = 37.037ns // Clock 27MHz => periode = 37ns
always #18 clk = ~clk; always #18 clk = ~clk;
ultrasonic_fpga uut ( ultrasonic_fpga uut (