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forked from tanchou/Verilog

5 Commits

Author SHA1 Message Date
Gamenight77
66fa5b2650 Add initial design files for 27 MHz clock counter
- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs.
- Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.
2025-04-15 08:59:40 +02:00
Gamenight77
7c09418828 Training exercise 2025-03-22 18:44:25 +01:00
e651a94dbe First simulation 2025-03-22 10:19:11 +01:00
Gamenight77
2c08e4bbbe Remove unnecessary closing parenthesis in counter module 2025-03-22 10:11:16 +01:00
Gamenight77
7bd92ebe98 counter 2025-03-22 09:50:52 +01:00