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forked from tanchou/Verilog
Commit Graph

8 Commits

Author SHA1 Message Date
Gamenight77 1d39c68b5c Refactor uart_tx module to implement FIFO functionality with write and read pointers 2025-05-05 15:29:45 +02:00
Gamenight77 7156abf4e7 Add UART TX module and testbench, update scripts and constraints 2025-05-05 15:23:44 +02:00
Gamenight77 e0a54fb42a Add LED indication for RX signal in top_uart_loopback module 2025-05-05 14:54:40 +02:00
Gamenight77 589c36ed83 Loopback ne fonctionne pas 2025-05-05 14:52:01 +02:00
Gamenight77 87732dcf87 uart modules work 2025-05-05 09:58:19 +02:00
Gamenight77 fc48941459 uart_rx valid 2025-05-05 09:51:23 +02:00
Gamenight77 c9a5fba97e TX tested with other's rx code (its work) 2025-05-05 09:26:41 +02:00
Gamenight77 f5e73d7379 struct 2025-05-02 15:51:18 +02:00