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forked from tanchou/Verilog
Commit Graph

2 Commits

Author SHA1 Message Date
Gamenight77
a00122b595 Fix clock period comment in testbench for clarity 2025-04-16 13:32:08 +02:00
Gamenight77
c8f108e01d Add Ultrasonic FPGA module and simulation testbench
- Implemented the ultrasonic_fpga module to handle ultrasonic sensor operations including triggering and measuring distance.
- Added a simulation testbench (ultrasonic_sim) to validate the functionality of the ultrasonic_fpga module.
- The module includes state management for triggering the sensor and measuring the echo duration to calculate distance.
- Simulation includes initialization, triggering the sensor, and checking the output distance.
2025-04-16 13:30:41 +02:00