Verilog

Commands

Compile code iverilog -o Nom_de_sortie.vvp .\source1.v .\tb_1.v

Upload on fpga

yosys -p "synth_ecp5 -json design.json" counter.v nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc