forked from tanchou/Verilog
c8f108e01d
- Implemented the ultrasonic_fpga module to handle ultrasonic sensor operations including triggering and measuring distance. - Added a simulation testbench (ultrasonic_sim) to validate the functionality of the ultrasonic_fpga module. - The module includes state management for triggering the sensor and measuring the echo duration to calculate distance. - Simulation includes initialization, triggering the sensor, and checking the output distance.
Verilog
Commands
Compile code iverilog -o Nom_de_sortie.vvp .\source1.v .\tb_1.v
Upload on fpga
yosys -p "synth_ecp5 -json design.json" counter.v nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc