forked from tanchou/Verilog
c8f108e01d
- Implemented the ultrasonic_fpga module to handle ultrasonic sensor operations including triggering and measuring distance. - Added a simulation testbench (ultrasonic_sim) to validate the functionality of the ultrasonic_fpga module. - The module includes state management for triggering the sensor and measuring the echo duration to calculate distance. - Simulation includes initialization, triggering the sensor, and checking the output distance.
74 lines
1.5 KiB
Verilog
74 lines
1.5 KiB
Verilog
`timescale 1ns/1ps
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module tb_ultrasonic_fpga;
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reg clk = 0;
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reg rst = 1;
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reg start = 0;
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reg echo = 0;
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wire trig_out;
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wire [15:0] distance;
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time t_start, t_end;
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// Clock 27MHz => periode = 37.037ns
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always #18 clk = ~clk;
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ultrasonic_fpga uut (
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.clk(clk),
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.rst(rst),
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.start(start),
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.echo(echo),
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.trig_out(trig_out),
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.distance(distance)
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);
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initial begin
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$dumpfile("ultrasonic.vcd");
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$dumpvars(0, tb_ultrasonic_fpga);
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// Reset
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#100;
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rst = 0;
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// Start
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#100;
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start = 1;
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#40;
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start = 0;
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wait (trig_out == 1);
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t_start = $time;
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// Attendre qu'il redescende
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wait (trig_out == 0);
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t_end = $time;
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$display("Trig HIGH duration: %0dns", t_end - t_start);
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if ((t_end - t_start) >= 9500 && (t_end - t_start) <= 10500) begin
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$display("Trigger signal is high for 10us.");
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#10;
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echo = 1;
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#5800;// Echo dure 5800ns (≈ 100 cycles @ 27MHz => ≈ 100 cm aller-retour)
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echo = 0;
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end else begin
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$display("Trigger signal is NOT high for 10us.");
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end
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#500;
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// Affiche la distance
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if (distance > 0) begin
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$display("Distance measured: %d cm", distance);
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end else begin
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$display("No distance measured.");
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end
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$finish;
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end
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endmodule
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