Verilog_Louis/README.md

# Verilog


## Commands
Compile code
iverilog -o Nom_de_sortie.vvp .\source1.v .\tb_1.v


### Upload on fpga
yosys -p "synth_ecp5 -json design.json" counter.v
nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc
Initial commit 2025-03-22 09:16:50 +01:00			`# Verilog`

Add Ultrasonic FPGA module and simulation testbench - Implemented the ultrasonic_fpga module to handle ultrasonic sensor operations including triggering and measuring distance. - Added a simulation testbench (ultrasonic_sim) to validate the functionality of the ultrasonic_fpga module. - The module includes state management for triggering the sensor and measuring the echo duration to calculate distance. - Simulation includes initialization, triggering the sensor, and checking the output distance. 2025-04-16 13:30:41 +02:00

			`## Commands`
			`Compile code`
			`iverilog -o Nom_de_sortie.vvp .\source1.v .\tb_1.v`


Add initial design files for 27 MHz clock counter - Created tangnano20k.cst to define I/O locations for clock, button, and LEDs. - Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output. 2025-04-15 08:59:40 +02:00			`### Upload on fpga`
			`yosys -p "synth_ecp5 -json design.json" counter.v`
			`nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc`