Verilog_Louis/Semaine_4/UART/src/verilog/top_uart_loopback.v

module top_uart_loopback (
    input wire clk, // 27 MHz
    input wire rx,
    output wire tx,
    output reg [5:0] leds
);

    wire rx_received;
    wire [7:0] rx_data;
    reg [7:0] tx_data;
    reg tx_enable;

    wire tx_ready;

    initial begin
        leds = 6'b111111;
    end

    // === UART RX ===
    other_uart_rx uart_rx_inst (
        .clk(clk),
        .rst_n(1'b1),
        .rx_pin(rx),
        .rx_data_valid(rx_received),
        .rx_data_ready(1'b1),
        .rx_data(rx_data)
    );

    // === UART TX ===
    other_uart_tx uart_tx_inst (
        .clk(clk),
        .rst_n(1'b1),
        .tx_data(tx_data),
        .tx_data_valid(tx_enable),
        .tx_data_ready(tx_ready),
        .tx_pin(tx)
    );

    // === FSM avec délai ===
    localparam IDLE = 0, WAIT = 1, SEND = 2;
    reg [1:0] state = IDLE;
    reg [8:0] delay_counter = 0; 

    always @(posedge clk) begin
        leds[5] <= rx;
        leds[4] <= tx;

        case (state)
            IDLE: begin
                tx_enable <= 0;
                delay_counter <= 0;

                if (rx_received && tx_ready) begin
                    tx_data <= rx_data;
                    state <= WAIT;

                    leds[0] <= 0;
                    leds[1] <= 1;
                end
            end

            WAIT: begin
                if (tx_ready) begin
                    tx_enable <= 1; 
                    state <= SEND;
                end else begin
                    tx_enable <= 0; 
                end
            end

            SEND: begin
                if (!tx_ready) begin // Attendre que la transmission commence
                    tx_enable <= 0;
                end else if (tx_ready && tx_enable == 0) begin
                    state <= IDLE; // Transmission terminée, retour à l’attente
                end

                leds[0] <= 0;
                leds[1] <= 0;
            end
        endcase
    end


endmodule