cac1a38dad
Leds
2025-05-26 11:18:25 +02:00
Gamenight77
a02d6e7d22
init semaine 7
2025-05-25 19:04:56 +02:00
4c3e40b266
Refactor FIFO module: update pointer and count handling for improved functionality
2025-05-22 14:49:36 +02:00
54bf6df85b
Add DHT11 UART communication module and related components
...
- Implemented a FIFO buffer in Verilog for data storage.
- Created a simplified UART transmitter (txuartlite) for serial communication.
- Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow.
- Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission.
- Added a testbench (tb_dht11) for simulating the DHT11 module functionality.
- Updated README with project description and command references.
- Created build and simulation scripts for both Linux and Windows environments.
- Added constraints file for hardware configuration.
- Implemented a state machine for managing measurement and data transmission.
2025-05-22 12:27:16 +02:00
Gamenight77
a541e033d7
Refactor DHT11 model: update clock comment for clarity and adjust state machine comment formatting
2025-05-22 08:58:27 +02:00
Gamenight77
434381e9b6
Refactor DHT11 module and testbench: update timing parameters, adjust state machine, and correct simulation script paths
2025-05-21 18:11:28 +02:00
cbebf620d5
Add DHT11 interface and model, update testbench and scripts for simulation
2025-05-20 15:55:21 +02:00
b3e646d854
Refactor ultrasonic modules and testbench for improved functionality and clarity
2025-05-20 14:24:41 +02:00
Gamenight77
436edae734
Add ultrasonic sensor model and driver, update testbench and scripts
2025-05-19 11:42:28 +02:00
Gamenight77
9755b1b0a3
Refactor testbench by removing unused sensor distance checks and simplifying LED verification logic
2025-05-19 09:53:24 +02:00
Gamenight77
1006b77e95
Update testbench and simulation scripts to use a unified output file name for GTKWave
2025-05-19 09:31:53 +02:00
Gamenight77
75d1ff029b
Semaine 6 init
2025-05-19 09:14:04 +02:00
Gamenight77
6ad0716f8f
Fix path in build script and improve comments in testbench for ultrasonic commands
2025-05-16 17:06:57 +02:00
Gamenight77
933f38d071
Merge branch 'main' of https://grond.iut-fbleau.fr/tanchou/Verilog
2025-05-16 10:34:35 +02:00
Gamenight77
e66a464812
Sa a l'air de fonctionner
2025-05-16 10:34:32 +02:00
3569b55925
Refactor project scripts for Windows and Linux: update paths and create new scripts for build, clean, simulate, and GTKWave functionalities.
2025-05-15 09:26:34 +02:00
abdc824c6d
Script pour linux structure
2025-05-15 09:23:21 +02:00
Gamenight77
861c9869f5
Add DHT11 interface and UART integration for ultrasonic sensor project
...
- Created DHT11 interface in Verilog to handle communication with DHT11 sensor.
- Implemented LED control logic to indicate sensor status and data readiness.
- Added project scripts for building, cleaning, and simulating the design.
- Established constraints for FPGA pin assignments.
- Developed testbench for DHT11 UART communication.
- Updated README files to reflect project functionality and commands.
2025-05-14 14:40:16 +02:00
Gamenight77
6a5b90c8d1
Refactor DHT11 interface: change output wires to registers for data ready, busy, and error signals
2025-05-14 10:31:48 +02:00
Gamenight77
2a153aa1eb
Enhance DHT11 interface: add start signal and busy output, improve FSM for better data handling
2025-05-14 10:27:46 +02:00
Gamenight77
1d6677d67d
Init du DHT11 Interface
2025-05-14 09:22:07 +02:00
Gamenight77
e124c7c0c4
Bloquer a cause du tx
2025-05-13 12:22:50 +02:00
Gamenight77
d1f907f7b6
Remove unnecessary IDE configuration files from the Python test directory
2025-05-13 10:21:47 +02:00
Gamenight77
b7d184d02f
Gros patch sur la fifo et rx fifo pour gagner des tick d'horloge, uart comand fonctionne toujours pas
2025-05-13 10:21:28 +02:00
Gamenight77
cca81f4db5
Fix formatting and update LED assignment in top_uart_ultrason_command module
2025-05-12 20:40:21 +02:00
Gamenight77
2cb68ce0d1
Debg compliqué
2025-05-12 15:34:02 +02:00
Gamenight77
790b85841b
Refactor UART testbench for ultrasonic commands: improve readability and organization of code structure
2025-05-12 13:24:58 +02:00
Gamenight77
30bbe27510
ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer
2025-05-12 12:15:52 +02:00
Gamenight77
004def5ba2
Add README for UART loopback issue and delay explanation
2025-05-09 11:58:55 +02:00
Gamenight77
e086ba8ef0
Loopback fifo fonctionne mais avec 3 valeur de décalage
2025-05-09 11:39:40 +02:00
Gamenight77
134df27937
Update README to include corrections and testing notes for FIFO and UART modules
2025-05-09 10:29:20 +02:00
Gamenight77
99e259f672
MAJ FIFO -> turn wire rd_data into register
2025-05-09 10:27:13 +02:00
Gamenight77
cd14d82add
patch
2025-05-09 09:20:56 +02:00
Gamenight77
a162a2a1bb
Update LED display logic to show received data instead of received signal
2025-05-09 09:15:44 +02:00
Gamenight77
a792f85adf
loopback fonctionne avec le rxuartlite
2025-05-09 09:15:28 +02:00
Gamenight77
93e0e96798
Add WAIT state to FSM and implement delay mechanism in UART module
2025-05-07 18:07:45 +02:00
Gamenight77
6bb42700f8
Update TX data assignment in UART loopback module to send fixed value
2025-05-07 18:05:02 +02:00
Gamenight77
f990a6f6d3
Fix UART RX module instantiation and update build script for correct file references
2025-05-07 11:07:42 +02:00
Gamenight77
83c40bee28
Fix build script and update state machine in UART loopback module
2025-05-07 10:39:52 +02:00
Gamenight77
ec1c69cf8f
Implement UART and ultrasonic sensor integration with FIFO for data transmission
2025-05-07 10:27:17 +02:00
Gamenight77
abef18227c
Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality
2025-05-07 09:46:43 +02:00
Gamenight77
86d4f5ddd2
rx fifo et tx fifo on l'air de fonctionner lors des testbenchs
2025-05-06 10:59:08 +02:00
Gamenight77
1ca3456ab8
Création de la structure du uart fifo
2025-05-06 09:42:26 +02:00
Gamenight77
aaebf22d48
Tb for fifo working fine
2025-05-06 09:14:59 +02:00
Gamenight77
1d39c68b5c
Refactor uart_tx module to implement FIFO functionality with write and read pointers
2025-05-05 15:29:45 +02:00
Gamenight77
7156abf4e7
Add UART TX module and testbench, update scripts and constraints
2025-05-05 15:23:44 +02:00
Gamenight77
e0a54fb42a
Add LED indication for RX signal in top_uart_loopback module
2025-05-05 14:54:40 +02:00
Gamenight77
589c36ed83
Loopback ne fonctionne pas
2025-05-05 14:52:01 +02:00
Gamenight77
87732dcf87
uart modules work
2025-05-05 09:58:19 +02:00
Gamenight77
fc48941459
uart_rx valid
2025-05-05 09:51:23 +02:00
