forked from tanchou/Verilog
66fa5b2650
- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs. - Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.
7 lines
168 B
Markdown
7 lines
168 B
Markdown
# Verilog
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## Command
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### Upload on fpga
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yosys -p "synth_ecp5 -json design.json" counter.v
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nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc
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