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forked from tanchou/Verilog
Commit Graph

11 Commits

Author SHA1 Message Date
Gamenight77
6dfd8768a0 Add testbench for top_ultrasonic_led module
- Created a new testbench file `top_ultrasonic_led_tb.vvp` to simulate the functionality of the `top_ultrasonic_led` module.
- Included necessary signal definitions and event triggers for clock, reset, start, echo, and trigger signals.
- Implemented a state machine to handle the ultrasonic measurement process and LED display logic.
- Added simulation parameters for distance measurement and LED control.
- Integrated VPI calls for waveform dumping and simulation control.
2025-04-16 14:58:04 +02:00
Gamenight77
7a2fbc0195 Add testbench for top_ultrasonic_led module
- Created a new testbench file `top_ultrasonic_led_tb.vvp` to simulate the `top_ultrasonic_led` module.
- Defined the necessary signals and events for testing the ultrasonic sensor functionality.
- Implemented the main test sequence including triggering the ultrasonic sensor and monitoring the output LEDs based on distance measurements.
- Included timing and state management for accurate simulation of the ultrasonic sensor behavior.
2025-04-16 14:23:18 +02:00
Gamenight77
079159bdb8 Refactor distance data type from 15 bits to 9 bits in ultrasonic_fpga module and update related testbench for consistency 2025-04-16 14:03:48 +02:00
Gamenight77
a00122b595 Fix clock period comment in testbench for clarity 2025-04-16 13:32:08 +02:00
Gamenight77
c8f108e01d Add Ultrasonic FPGA module and simulation testbench
- Implemented the ultrasonic_fpga module to handle ultrasonic sensor operations including triggering and measuring distance.
- Added a simulation testbench (ultrasonic_sim) to validate the functionality of the ultrasonic_fpga module.
- The module includes state management for triggering the sensor and measuring the echo duration to calculate distance.
- Simulation includes initialization, triggering the sensor, and checking the output distance.
2025-04-16 13:30:41 +02:00
Gamenight77
66fa5b2650 Add initial design files for 27 MHz clock counter
- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs.
- Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.
2025-04-15 08:59:40 +02:00
Gamenight77
7c09418828 Training exercise 2025-03-22 18:44:25 +01:00
e651a94dbe First simulation 2025-03-22 10:19:11 +01:00
Gamenight77
2c08e4bbbe Remove unnecessary closing parenthesis in counter module 2025-03-22 10:11:16 +01:00
Gamenight77
7bd92ebe98 counter 2025-03-22 09:50:52 +01:00
8e7615d669 Initial commit 2025-03-22 09:16:50 +01:00