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forked from tanchou/Verilog
Commit Graph

10 Commits

Author SHA1 Message Date
Gamenight77 c6d33d278e Implement distance measurement and display modules: add ultrasonic sensor, FPGA logic, LED display, and WS2812 driver for enhanced distance visualization 2025-04-25 10:21:18 +02:00
Gamenight77 eecf17f45d Refactor ultrasonic sensor module: implement echo signal handling and state management for improved distance measurement 2025-04-25 09:46:08 +02:00
Gamenight77 bc7518a231 Refactor ultrasonic FPGA module: add echo_div_counter and distance_counter for improved distance measurement logic 2025-04-25 09:23:33 +02:00
Gamenight77 d8708d1bd5 Refactor ultrasonic FPGA module: replace sig_in with sig_ok for improved signal handling and update ESP32 command processing to support new client list command 2025-04-25 09:17:22 +02:00
Gamenight77 2b7582808e Update serial communication code: change COM port in read_rx.py and add ESP32 command interpretation in esp32_read.py 2025-04-23 11:50:26 +02:00
Gamenight77 73cc201b6d Add README and project documentation for FPGA and ESP32 integration 2025-04-22 16:46:03 +02:00
Gamenight77 8641f618f0 Refactor uart_top module: streamline code structure and improve readability by removing unused variables and simplifying instantiation 2025-04-22 15:44:04 +02:00
Gamenight77 5f3568ff9b Enhance ultrasonic_fpga module: add comment to clarify FSM behavior in the Verilog file 2025-04-22 14:40:12 +02:00
Gamenight77 2be0cb20f6 Refactor ultrasonic_fpga module: improve code readability by adjusting comments and formatting in the Verilog file. 2025-04-22 14:38:50 +02:00
Gamenight77 3bb56e2f57 Init et début de réflexion sur le projet 2025-04-22 09:56:06 +02:00