verlan/Verilog_Louis
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Code Pull Requests Activity

Commit Graph

  • 55f9161dfa Add UART transmitter module and testbench Gamenight77 2025-04-17 10:56:16 +02:00
  • d46530f32d Add memo.png image file for UART module documentation Gamenight77 2025-04-17 09:08:24 +02:00
  • fd09bb30e3 Add distance_ws2812_display module and testbench; implement ws2812_driver for LED control Gamenight77 2025-04-16 17:07:29 +02:00
  • 6dfd8768a0 Add testbench for top_ultrasonic_led module Gamenight77 2025-04-16 14:58:04 +02:00
  • 7a2fbc0195 Add testbench for top_ultrasonic_led module Gamenight77 2025-04-16 14:23:18 +02:00
  • 079159bdb8 Refactor distance data type from 15 bits to 9 bits in ultrasonic_fpga module and update related testbench for consistency Gamenight77 2025-04-16 14:03:48 +02:00
  • a00122b595 Fix clock period comment in testbench for clarity Gamenight77 2025-04-16 13:32:08 +02:00
  • c8f108e01d Add Ultrasonic FPGA module and simulation testbench Gamenight77 2025-04-16 13:30:41 +02:00
  • 66fa5b2650 Add initial design files for 27 MHz clock counter Gamenight77 2025-04-15 08:59:40 +02:00
  • 7c09418828 Training exercise Gamenight77 2025-03-22 18:44:25 +01:00
  • e651a94dbe First simulation Louis TANCHOU 2025-03-22 10:19:11 +01:00
  • 2c08e4bbbe Remove unnecessary closing parenthesis in counter module Gamenight77 2025-03-22 10:11:16 +01:00
  • 7bd92ebe98 counter Gamenight77 2025-03-22 09:50:52 +01:00
  • 8e7615d669 Initial commit Louis TANCHOU 2025-03-22 09:16:50 +01:00